1. Field of the Invention
Embodiments of the invention relate to a method of manufacturing a semiconductor device. More particularly, embodiments of the invention are directed to a method of thermally processing a substrate.
2. Background
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. One of the major steps the industry has taken to address these demands is to change from batch processing silicon wafers in large furnaces to single wafer processing in a small chamber.
During such single wafer processing the wafer is typically heated to high temperatures so that various chemical and physical reactions can take place in multiple IC devices defined in the wafer. Of particular interest, favorable electrical performance of the IC devices requires implanted regions to be annealed. Annealing recreates a more crystalline structure from regions of the wafer that were previously made amorphous, and activates dopants by incorporating their atoms into the crystalline lattice of the substrate, or wafer. Thermal processes, such as annealing, require providing a relatively large amount of thermal energy to the wafer in a short amount of time, and thereafter rapidly cooling the wafer to terminate the thermal process. Examples of thermal processes currently in use include Rapid Thermal Processing (RTP) and impulse (spike) annealing. While such processes are widely used, current technology is not ideal for large substrates which tend to be exposed to elevated temperatures for a long time period. These problems become more severe with increasing switching speeds and/or decreasing feature sizes.
In general, these thermal processes heat the substrates under controlled conditions according to a predetermined thermal recipe. These thermal recipes fundamentally consist of a temperature that the semiconductor substrate must be heated to the rate of change of temperature, i.e., the temperature ramp-up and ramp-down rates and the time that the thermal processing system remains at a particular temperature. For example, some thermal recipes may require the entire substrate to be heated from room temperature to a temperature of 400° C. or more for processing times that exceed the thermal budget of the devices formed on the substrate.
Moreover, to meet certain objectives, such as minimal inter-diffusion of materials between different regions of a semiconductor substrate, the amount of time that each semiconductor substrate is subjected to high temperatures must be restricted. To accomplish this, the temperature ramp rates, both up and down, are preferably high. In other words, it is desirable to be able to adjust the temperature of the substrate from a low to a high temperature, or visa versa, in as short a time as possible.
The requirement for high temperature ramp rates led to the development of Rapid Thermal Processing (RTP), where typical temperature ramp-up rates range from 200 to 400° C./s, as compared to 5-15° C./minute for conventional furnaces. Typical ramp-down rates are in the range of 80-150° C./s. A drawback of RTP is that it heats the entire wafer even though the IC devices reside only in the top few microns of the silicon wafer. This limits how fast one can heat up and cool down the wafer. Moreover, once the entire wafer is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, today's state of the art RTP systems struggle to achieve a 400° C./s ramp-up rate and a 150° C./s ramp-down rate.
As device sizes on substrates grow smaller in the future, thermal budgets must reduce as well, because smaller devices may be degraded more easily by inter-diffusion of materials. Temperature ramp-up and ramp-down rates must be increased to compress anneal times, for example below one second.
To resolve some of the problems raised in conventional RTP type processes, various scanning laser anneal techniques have been used to anneal the surface(s) of the substrate. In general, these techniques deliver a constant energy flux to a small region on the surface of the substrate while the substrate is translated, or scanned, relative to the energy delivered to the small region. Other laser scanning processes hold the substrate still and move the laser across the substrate surface. Due to the stringent uniformity requirements and the complexity of minimizing the overlap of scanned regions across the substrate surface, these types of processes are not effective for thermal processing contact level devices formed on the surface of the substrate. Additionally, thermal stresses generated in the substrate by the high thermal gradients associated with extreme localized heating may result in damage to the substrate.
In view of the above, there is a need for novel apparatuses and methods for annealing a semiconductor substrate with high ramp-up and ramp-down rates. This will offer greater control over the fabrication of smaller devices leading to increased performance.